1. Field
Example embodiments relate to Error Control Codes (ECC). Also, example embodiments relate to ECC apparatuses and methods that can determine whether to bypass a portion of ECC blocks, depending on an error level generated in a channel, and can control ECC performance.
2. Description of Related Art
When error levels generated in a channel are different, an optimized ECC structure is generally embodied depending on an error level.
Specifically, when the error level generated in the channel is low, the error level may be corrected using one ECC block. Also, when the error level generated in the channel is high, the error level may be corrected using one ECC block. However, since high-level error correction capacity using one ECC block is required when the error level generated in the channel is high, an ECC structure having high-level complexity is required.
Accordingly, when the error level generated in the channel is high, a concatenated ECC structure, which may have identical performance with generally low complexity compared with using one ECC block, is used.
However, since an ECC calculation is performed using all ECC blocks regardless of an error level of a channel side, latency is unnecessarily lengthened, unnecessary power consumption is generated, and an unnecessary redundancy data transmission is required when the error level of the channel side is lowered. Accordingly, a ratio of an information amount to a total code length, that is, a code rate is unnecessarily reduced.
Also, when the error level generated in the channel side is low, the ECC structure including one ECC block is used, and when the error level generated in the channel side is high, two structures may be configured together in order to use the concatenated ECC structure. However, complexity of a circuit is increased in this case.
Accordingly, an apparatus which can reduce complexity and control ECC performance depending on an error level generated in a channel is required.